The present invention relates to a technique for fabricating electrically conductive paths through a semiconductor wafer. More specifically, the invention discloses a process for forming electroplated via holes through a compound semiconductor substrate.
Conductive via holes are conventionally used as a means for interconnecting regions on one surface of a printed circuit board to regions on the opposing surface of the circuit board. Reference can be made to U.S. Pat. No. 3,799,802, PLATED THROUGH HOLE PRINTED CIRCUIT BOARDS, F. W. Schneble, Jr. et al, issued Mar. 26, 1974, for an elaboration of such a process. In the fabrication of semiconductor devices it also, on occasion, becomes desirable to form a circuit pattern on the "front side" of a wafer, a pattern on the "back side" of the wafer, and via hole interconnections between the two patterns. For example, in the fabrication of microwave devices it might be desirable to form a field effect transistor (FET) or diode on a first surface of a compound semiconductor wafer, a microstrip, heat sink, or ground plane on the opposing semiconductor surface, and a via hole interconnection between both sides. An example of this type of structure is described in copending U.S. patent application Ser. No. 192,849, MONOLITHIC INTEGRATED CIRCUIT, filed Oct. 1, 1980, by R. L. Camisa.
In the conventional fabrication sequence for a microwave device, various electronic components are first fabricated on the "front side" surface of a III-V material such as gallium arsenide. Photolithographic processing is then performed on the "back side" of the wafer so as to precisely align via hole locations on the back side to circuit features on the front side. A suitable chemical etchant is then applied to the back side, ultimately resulting in a tapered via hole projecting through the wafer. Following the etching, metallization is applied so as to form an electrically conductive connection through the wafer. Further elaboration of a conventional processing sequence is disclosed in U.S. Pat. No. 3,986,196, THROUGH-SUBSTRATE SOURCE CONTACT FOR MICROWAVE FET, issued Oct. 12, 1976, to D. R. Decker et al.
There are certain problem areas, however, in conventional conductive via hole processing. The process of aligning a hole pattern on the back side of the wafer to a circuit pattern on the front side of the wafer requires the use of expensive, precision equipment. Additionally, the chemical etching of the via holes produces significant undercutting of wafer material, the extent of the undercutting typically being proportional to the depth of the etched hole. In our experience, attempts to form a 1 mil diameter via hole in a 4 mil thick GaAs wafer, yields a via hole having a 4-5 mil diameter on the back side of the wafer. Furthermore, when there are a plurality of via holes on a particular wafer, the holes typically do not all etch at the same rate, producing a significant variance in dimension among via holes.
In an attempt to overcome the problems associated with chemical etching, we attempted to laser drill the holes directly on the front side wafer surface. However, this technique proved unsatisfactory because of the considerable surface damage the laser drilling introduced to the wafer. In an attempt to overcome these problems, the present invention was discovered.